A VHDL common library built to simplify and speed up the development of FPGA project

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Aurnytoraink 1432c81c42 Clock edge can be selected		2026-04-08 15:17:57 +02:00
ip/Async_FIFO	Clock edge can be selected	2026-04-08 15:17:57 +02:00
MAIN.vhd	Added new conversion function	2026-03-27 15:24:03 +01:00
README.md	Added Asynchronous FIFO IP	2026-03-27 15:33:47 +01:00

README.md

LIB_COMMON

A common VHDL library meant to simplify and speed up the development of FPGA project.

This library comes with a set of predefined types and functions, so you don't have to manually copy them, each time you create a new project or module.

This library also provides basic common IPs such as Asynchronous FIFO

How to use ?

Inside your IDE, create a new library lib_common
Import the needed file(s) to your project
Inside your IP, import the package

library LIB_COMMON;
use LIB.COMMON.MAIN.all; -- mandatory
use LIB.COMMON.XXX.all;